FS-1052: Contents

CONTENTS

LETTER OF PROMULGATION

Forward

Figures

Tables

1. SCOPE

1.1 Limitations
1.2 Application
1.3 System standard and design objective (DO)

2. REFERENCED DOCUMENTS

2.1 Governmental
2.2 Non-governmental
2.3 Order of precedence

3. DEFINITIONS

3.1 Terms
3.2 Abbreviations and acronyms

4. GENERAL REQUIREMENTS

4.1 General system description
4.2 Common parameters
4.2.1 User data rates
4.2.2 Logic and signaling sense for binary signals
4.2.3 Digital interface characteristics
4.2.4 Terminal impedance for quasi-analog signals
4.2.5 Quasi-analog signal levels
4.2.6 Clock equipment, control, and timing
4.3 General design requirements
4.3.1 Federal maritime interoperability requirements
4.3.2 International interoperability requirements
4.3.2.1 Shore-to-ship broadcast systems
4.3.2.2 Maritime air communications systems
4.3.2.3 Radio teletypewriter systems

5. DETAILED REQUIREMENTS

5.1 HF data modems
5.1.1 General requirements
5.1.1.1 Capability
5.1.1.2 Voice digitization
5.1.1.3 Optional modes
5.2 Interface requirements
5.2.1 Data terminal equipment (DTE) interface
5.2.1.1 Circuits supported - all modes
5.2.1.2 Circuits supported - synchronous modes
5.2.1.3 Interface features
5.2.1.3.1 Receive data transmit MARK hold
5.2.1.3.2 Receive data no-signal MARK hold
5.2.2 Analog interface
5.2.2.1 Modulator output
5.2.2.2 Demodulator input
5.2.3 Equipment-side characteristics
5.3 Frequency-shift keying (FSK) waveform
5.3.1 Capability
5.3.2 Code transparency
5.3.3 FSK tone frequencies
5.3.4 FSK adaptive tone selection
5.3.4.1 Receive signal requirements
5.3.4.2 Receive signal polarity, code, and protocol
5.3.4.3 Modulator tone frequencies
5.3.4.4 Adaptive tone selection operation
5.4 Serial (single-tone) mode
5.4.1 General
5.4.1.1 Data conversion and modulation
5.4.1.2 Nonsynchronous data operation
5.4.2 Sequencing of time phases
5.4.2.1 Synchronization (sync) preamble phase
5.4.2.2 Data phase
5.4.2.3 EOM phase
5.4.2.4 FEC coder and interleaver flush phase
5.4.3 Functional descriptions
5.4.3.1 EOM sequence
5.4.3.2 Interleaver flush
5.4.3.3 FEC encoder
5.4.3.4 Interleaver load
5.4.3.5 Interleaver fetch
5.4.3.6 Modified-Gray decoder (MGD)
5.4.3.7 Symbol formation
5.4.3.7.1 Symbol formation for data transmission
5.4.3.7.1.1 Unknown data
5.4.3.7.1.2 Known data
5.4.3.7.2 Sync preamble sequence
5.4.3.7.2.1 General
5.4.3.7.2.2 Preamble pattern generation
5.4.3.8 Scrambler
5.4.3.8.1 Data sequence randomizing generator
5.4.3.8.2 Sync sequence randomizing generator
5.4.3.9 PSK modulation
5.4.4 Waveform summary
5.4.5 Performance requirements

6. EFFECTIVE DATE

7. CHANGES

APPENDIX A, 39-TONE PARALLEL MODE

10. GENERAL

10.1 Scope
10.2 Applicability

20. APPLICABLE DOCUMENTS

30. DEFINITIONS

40. GENERAL REQUIREMENTS

50. DETAILED REQUIREMENTS

50.1 Characteristics
50.2 Error-correcting coding
50.3 Interleaving
50.4 Synchronization
50.4.1 Preamble
50.4.2 Extended preamble
50.4.3 Data block synchronization
50.5 Modulator output signal
50.6 In-band diversity
50.6.1 Time/frequency diversity
50.6.2 Frequency diversity
50.7 Asynchronous data operation
50.7.1 Character length
50.7.2 Data signaling rate constraint
50.7.3 Data-rate adjustment
50.7.3.1 Input data source rate greater than modem rate
50.7.3.2 Input data source rate less than modem rate
50.7.4 End-of-message (EOM) indication
50.7.5 Asynchronous mode interleaving and block framing
50.7.6 Bit packing

60. PERFORMANCE REQUIREMENTS

APPENDIX B, DATA LINK PROTOCOL

10. GENERAL.

10.1 Scope
10.2 Applicability

20. APPLICABLE DOCUMENTS

30. DEFINITIONS

30.1 Terms
30.2 Abbreviations and acronyms

40. GENERAL REQUIREMENTS

40.1 Modes
40.1.1 ARQ mode
40.1.2 Broadcast mode
40.1.3 Circuit mode
40.2 Implementation
40.3 Functionality
40.3.1 Open Systems Interconnection (OSI) compatibility
40.3.2 Physical circuit
40.3.3 Priority
40.3.4 Preemption
40.3.5 Flow control
40.3.6 Channel optimization
40.3.7 Synchronization
40.3.8 Order of transmission

50. DETAILED REQUIREMENTS

50.1 Protocol frames
50.1.1 General frame format
50.1.1.1 Frame sync pattern
50.1.1.2 Sync Mismatch Bit
50.1.1.3 Frame Type bit
50.1.1.4 Frame Headers and Data.
50.1.1.5 CRC error control checksum
50.1.2 Control frame format
50.1.2.1 Control frame header fields
50.1.2.1.1 Protocol Version
50.1.2.1.2 Control Mode
50.1.2.1.3 Negotiation Mode
50.1.2.1.4 Extended Addressing
50.1.2.1.5 Source Address
50.1.2.1.6 Destination Address
50.1.3 Link management header fields
50.1.3.1 Link State
50.1.3.2 Link Timeout
50.1.4 Data transfer header fields
50.1.4.1 ACK/NAK Type
50.1.4.2 ACK Bit-Map/Extended Address
50.1.4.2.1 ACK Bit-Map field
50.1.4.2.1.1 ACK Bit-Map
50.1.4.2.1.2 Flow Control
50.1.4.2.1.3 Extended Address
50.1.4.3 Alternating Data-ACK Frames bit
50.1.5 Herald header fields
50.1.5.1 Data Rate Format
50.1.5.2 Data Rate
50.1.5.3 Interleaver Length
50.1.5.4 Number of Bytes in Data Frames
50.1.5.5 Number of Frames in Next Series
50.1.6 Message management header fields
50.1.6.1 Transmit Message ID
50.1.6.2 Transmit Connection ID
50.1.6.3 Transmit Message Size
50.1.6.4 Transmit Message Next Byte Location
50.1.6.5 Reserved (transmit)
50.1.6.6 Transmit Message Priority
50.1.6.7 Receive Message Next Byte Location
50.1.6.8 Reserved (receive)
50.1.7 Extended function header fields
50.1.7.1 User ID
50.1.7.2 Function Bits
50.2 Control frame lengths
50.2.1 Variable-length control frames
50.2.2 Fixed-length control frames
50.3 Data frame format
50.3.1 Reverse channel control frame fields
50.3.2 Data frame header fields.
50.3.2.1 Data Frame Sequence Number
50.3.2.2 Message Byte Offset
50.3.2.3 Reserved
50.3.3 Data field
50.4 Protocol suite
50.4.1 Message management protocol
50.4.1.1 Message announcement
50.4.1.2 Message acceptance
50.4.1.3 Message refusal
50.4.1.4 Priority resolution
50.4.1.5 Message preemption
50.4.1.5.1 Forward preemption
50.4.1.5.2 Reverse preemption
50.4.1.6 Message resumption
50.4.1.7 Null message management headers
50.4.2 Link establishment protocol
50.4.2.1 Link establishment states
50.4.2.1.1 Idle
50.4.2.1.2 Calling
50.4.2.1.3 Call acknowledge
50.4.2.1.4 Linked up state
50.4.2.2 Link failure
50.4.2.3 Link termination
50.4.2.4 Immediate mode
50.4.2.5 State sequence rules
50.4.3 Data transfer protocol
50.4.3.1 ARQ mode
50.4.3.1.1 Negotiation phase
50.4.3.1.1.1 Initiation
50.4.3.1.1.2 Acceptance
50.4.3.1.1.3 Data refusal
50.4.3.1.2 Data transfer phase
50.4.3.1.3 Data acknowledgment phase
50.4.3.1.4 Flow control
50.4.3.2 Broadcast mode
50.4.3.3 Circuit mode
50.4.4 Timeouts
50.4.4.1 Turn-around times
50.4.4.2 Response timeout
50.4.4.3 Link timeout
50.4.4.4 Action following timeout
50.4.5 Duplex operation
50.5 Examples

60. NOTES

60.1 Implementation guidelines
60.1.1 Adapting data rate
60.1.2 FED-STD-1052 serial (single-tone) interleaver capacity

APPENDIX C, SIXTEEN-TONE DIFFERENTIAL PHASE-SHIFT KEYING (DPSK) MODE

10. GENERAL

10.1 Scope
10.2 Applicability

20. APPLICABLE DOCUMENTS

30. DEFINITIONS

40. GENERAL REQUIREMENTS

40.1 Introduction
40.2 Input/output data signaling rates

50. DETAILED REQUIREMENTS

50.1 Modulator output signal
50.2 Data tone frequencies
50.3 Phase modulation and encoding
50.4 Synchronization
50.5 Doppler correction
50.6 In-band diversity combining
50.7 Demodulator signal alarm

FIGURES

Figure 1 Typical interface between data terminal equipment and data circuit-terminating equipment

Figure 2 Serial (single-tone) waveform functional block diagram

Figure 3 An example of equipment interface block diagram

Figure 4 FEC encoder block diagram

Figure 5 State constellation diagram

Figure 6 Randomizing shift register functional diagram

Figure 7 Transmit direction functional diagram

Figure 8 Data flow through encoder and interleaver for an interleaver containing an even number of code words

Figure 9 Data flow through encoder and interleaver for an interleaver containing an odd number of code words

Figure 10 Transmit sequence of events

Figure 11 Framing sequence feedback shift register generator

Figure 12 Basic protocol frame format

Figure 13 Control frame format

Figure 14 Extended addressing example: from ABCD to WXYZ

Figure 15 Control frames

Figure 16 Data frame format

Figure 17 State sequence, link establishment protocol

Figure 18 Examples of data transfers over the data link during DLP operation

Figure 19 Phase modulation vectors for 16-tone DPSK data modem

TABLES

Table I. Logic and signal sense for binary signals

Table II. Error-correcting coding

Table III. Interleaver matrix dimensions

Table IV. Bits-per-channel symbol

Table V. Modified-Gray decoding at 4800 b/s and 2400 b/s

Table VI. Modified-Gray decoding at 1200 b/s and 75 b/s

Table VII. Channel symbol mapping for 75 b/s

Table VIII. Assignment of designation symbols D1 and D2

Table IX. Conversion of two-bit count value to three-bit symbol

Table X. Channel symbol mapping for sync preamble

Table XI. Data phase waveform characteristics

Table XII. Serial (single-tone) mode minimum performance

Table XIII. Selectable interleaving degrees

Table XIV. Tone set application, amplitude, and phase

Table XV. Framing sequence insertion intervals and lengths

Table XVI. Data-tone frequencies and bit locations

Table XVII. Modulation characteristics of the 39-tone HF modem

Table XVIII. In-band time/frequency diversity

Table XIX. In-band frequency diversity

Table XX. Asynchronous character set

Table XXI. 75-b/s asynchronous operational parameters

Table XXII. 150-b/s asynchronous operational parameters

Table XXIII. 300-b/s asynchronous operational parameters

Table XXIV. 600-b/s asynchronous operational parameters

Table XXV. 1200-b/s asynchronous operational parameters

Table XXVI. 2400-b/s asynchronous operational parameters

Table XXVII. Probability of bit error vs signal-to-noise ratio

Table XXVIII.Code definitions for data-rate formats

Table XXIX. Maximum series size

Table XXX. Serial (single-tone) interleaver buffer capacity

Table XXXI. Data-tone frequencies and bit locations

Table XXXII. Modulation characteristics