FS-1052: Detailed Requirements

5. DETAILED REQUIREMENTS.

5.1 HF data modems. Both the frequency-shift keying (FSK) waveform and the serial (single-tone) transmit waveform described in this paragraph establish the minimum essential interoperability and performance requirements for new HF modems.

5.1.1 General requirements.

5.1.1.1 Capability. The HF modems shall be capable of modulating and demodulating serial binary data into/from an FSK waveform or a serial (single-tone) waveform. The waveform is transmitted/received over HF radio operating in a fixed-frequency mode of operation. The minimum acceptable performance and U.S. Government interoperability shall be at 75 b/s using the FSK and phase shift keying (PSK) serial (single-tone) waveforms specified herein. The following optional PSK serial (single-tone) rates, if selected for use, shall be incorporated in accordance with this standard: 150, 300, 600, 1200, 2400, all coded, and 4800 b/s uncoded. As a DO, at the rates above 75 b/s, the modem should have the capability to adapt to circuit conditions. The FED-STD-1052 serial (single-tone) modem (excluding the data link protocol) shall be interoperable with the MIL-STD-188-110A serial (single-tone) modem in the non-frequency hopping modes.

5.1.1.2 Voice digitization. When integrated within the data modem, the minimum mode for voice digitization functions shall be in accordance with (IAW) NATO STANAG 4198.

5.1.1.3 Optional modes. As a DO, the modem should be expandable to include one or more of the following optional modes:

a. NATO mode. If included, this mode shall be in accordance with STANAG 4285.
b. Advanced narrowband digital voice terminal (ANDVT) (thirty-nine-tone library used for secure voice and sixteen-tone subset of the thirty-nine-tone library used for data). If included, this mode shall be in accordance with MIL-C-28883 and STANAG 4197.
c. Thirty-nine-tone DPSK mode. If included, this mode shall be in accordance with appendix A.
d. Sixteen-tone differential phase-shift keying (DPSK) mode. If included, this mode shall be in accordance with appendix C.
e. Frequency hopping mode. If included, this mode shall be in accordance with the PSK serial (single-tone) waveform contained in MIL-STD-188-110A and the data training and timing format provided in MIL-STD-188-148A, Appendix D.

5.2 Interface requirements (optional).

5.2.1 Data terminal equipment (DTE) interface. The electrical characteristics of the digital interface signals shall be IAW FED-STD-1030, which implements EIA Standard 423, or ANSI/EIA/TIA-562. When the modem is provided with a hardware connection to an external DTE, it is recommended that the connectors, pin connections, and digital signal electrical interface signals should be IAW ANSI/EIA-232 (DB-25S connector) or ANSI/EIA/TIA-574 (DE-9S connector).

5.2.1.1 Circuits supported - all modes. The following circuits for both synchronous and nonsynchronous modes shall be supported as defined by FED-STD-1030 and ANSI/EIA-232 or ANSI/EIA/TIA-574:

a. Transmitted Data (input), Interchange Circuit (IC Ckt) BA.
b. Received Data (output), IC Ckt BB.
c. Signal Ground/Common Return, IC Ckt AB.
d. Received Line Signal Detector (carrier detect), IC Ckt CF.

5.2.1.2 Circuits supported - synchronous modes. (Optional for nonsynchronous modes)

a. Request to Send, IC Ckt CA.
b. Clear to Send, IC Ckt CB.
c. DCE Ready (data set ready), IC Ckt CC.
d. DTE Ready (data terminal ready), IC Ckt CD.

(The following are not supported by ANSI/EIA/TIA-574)

e. Transmitter Signal Element Timing (DTE) (external transmit clock), IC Ckt DA.
f. Transmitter Signal Element Timing (DCE) (transmit clock), IC Ckt DB.
g. Receiver Signal Element Timing (DCE) (receive clock), IC Ckt DD

NOTE: Frame or protective ground is not classified as an interchange circuit in the ANSI/EIA-232 standard.

5.2.1.3 Interface features. The following interface features are optional.

5.2.1.3.1 Receive data transmit MARK hold. In a half-duplex modem circuit, the receive data output may be held in the MARK signal condition when the modem is transmitting. This feature is not used when the modem operates in the full-duplex mode.

5.2.1.3.2 Receive data no-signal MARK hold. In a half-duplex modem circuit, the receive data output may be held in the MARK signal condition when the carrier detect (IC Ckt CF) is in the OFF condition.

5.2.2 Analog interface. When the modem provides hardware analog interface connections to external devices, the interface signals shall have the following characteristics.

5.2.2.1 Modulator output. The modulator output shall have an output impedance of 600 ohms (±10%), balanced and isolated, over the frequency range of operation. The modulator output level shall be adjustable over the range of -10 dBm to +3 dBm. A 150 ohm terminal impedance, unbalanced to ground, is optional.

5.2.2.2 Demodulator input. The demodulator input shall have an input impedance of 600 ohms (±10%), balanced and isolated, over the frequency range of operation. Demodulator performance shall be maintained with a nominal input level of -10 dBm to +3 dBm.

5.2.3 Equipment-side characteristics. Modems shall be designed to provide the required performance (see par. 5.4.5) using the single-channel bandwidth and characteristics as given in FED-STD-1045. As a DO, modems should be capable of transmitting and receiving the quasi-analog signals over unconditioned 3-kHz voice frequency (VF) lines while maintaining the performance established in par. 5.4.5.

5.3 Frequency-shift keying (FSK) waveform. The FSK transmit waveform described herein is mandatory. This requirement is intended to assure minimum essential interoperability with existing FSK HF modem equipment. This requirement will expire on 31 December 2001.

5.3.1 Capability. The FSK modems shall be capable of modulating and demodulating serial binary data (asynchronous, synchronous, or bit synchronous) into/from an FSK waveform. This waveform is transmitted/received over HF radio. The minimum acceptable performance and U.S. Government interoperability shall be at 75 Bd. Other data rates, consistent with par. 4.2.1, are optional. The external timing signal requirement (par. 4.2.6) shall be optional for the FSK modem.

5.3.2 Code transparency. The FSK waveform generated by the modulator shall be code transparent. Data input of the MARK state into the modulator shall produce an output of the FSK MARK frequency. Data input in the SPACE state shall produce an output at the FSK SPACE frequency. Reception of the FSK MARK frequency shall be demodulated to produce a MARK output data state. Reception of the SPACE frequency shall be demodulated to produce a SPACE data output state.

5.3.3 FSK tone frequencies. The MARK and SPACE FSK modulator and demodulator tone frequencies shall be independently adjustable over the frequency range of 1000 Hz to 3000 Hz in 5-Hz or less steps.

5.3.4 FSK adaptive tone selection. (Optional). The modem may include the capability to lock-on and adapt to the distant transmit modem MARK/SPACE frequencies.

5.3.4.1 Receive signal requirements. When adaptive tone selection is used, the parameters of the receive signal must be within the following limits:

a. FSK data rate of 75 Bd,
b. Tone frequency range of 1000 Hz to 3000 Hz,
c. FSK shift must be greater than the baud rate.

5.3.4.2 Receive signal polarity, code, and protocol. When adaptive tone selection is used, determination of the received signal's FSK MARK/SPACE polarity, code, and waveform protocol is made by equipment other than the FED-STD-1052 modem.

5.3.4.3 Modulator tone frequencies. When adaptive tone selection is used to set the demodulator FSK filter frequencies, the modulator section of the FED-STD-1052 modem shall be adjusted such that the transmitted MARK and SPACE tone frequencies match those selected for the demodulator.

5.3.4.4 Adaptive tone selection operation. The adaptive tone selection feature shall be selected manually by the operator or by devices external to the FED-STD-1052 modem. Adaptive tone search may be initiated by remote control command, by external signal input, or by a switch on the modem. Upon initiation, a FED-STD-1052 modem equipped for adaptive tone selection shall search the audio frequency spectrum between 1000 Hz and 3000 Hz. If distinctive MARK and SPACE FSK spectral distribution is discovered, the demodulator tone filters and the modulator transmit tones shall be set to the center frequencies of these distributions. Automatic frequency adjust capabilities shall then be disabled and the modem will function as a fixed-frequency FSK modem until the control input is again activated by the operator or external control device.

5.4 Serial (single-tone) mode.

5.4.1 General. This mode shall employ M-ary phase-shift keying (PSK) on a single carrier frequency as the modulation technique for data transmission.

5.4.1.1 Data conversion and modulation. Serial binary information accepted at the line-side input is converted into a single 8-ary PSK-modulated output carrier. The modulation of this output carrier shall be a constant 2400-symbols-per-second waveform regardless of the actual throughput rate. The rate-selection capability shall be as given in par. 5.1.1.1. Selectable interleaver settings shall be provided.

5.4.1.2 Nonsynchronous data operation. (Optional). In addition to bit-synchronous data transmission, a nonsynchronous mode shall also be supported. When operating in the nonsynchronous mode, the modulator shall accept source data in nonsynchronous start/parity/stop character format. The start/parity/stop bits shall be included in the bit stream which is provided to the forward error correction (FEC) encoder. MARK (1) bits shall be inserted in the bit stream as necessary to maintain a bit-synchronous data stream to the FEC encoder. The demodulator will deliver data in nonsynchronous start/parity/stop character format to the receiving data terminal equipment (DTE).

5.4.2 Sequencing of time phases. The PSK waveform (signal structure) has four functionally distinct, sequential transmission phases. These time phases are:

a. Synchronization preamble phase.
b. Data phase.
c. End-of-message (EOM) phase.
d. Coder and interleaver flush phase.

Figure 2 is the functional block diagram.

Figure 2. Serial (single-tone) waveform functional block diagram

5.4.2.1 Synchronization (sync) preamble phase. The duration of the sync preamble phase shall correspond to the exact time required to load the selected interleaver matrix, when an interleaver is present, with one block of data. During this phase, switch S1 (see Fig. 2) shall be in the UNKNOWN DATA position and the encode and load interleave functions shall be active as the modem begins accepting data from the DTE. Switches S2 and S3 shall be in the SYNC position. The transmitting modem shall send the required sync preamble sequence (see par. 5.4.3.7.2) to achieve time and frequency sync with the receiving modem. The length of the sync preamble sequence pattern shall be 0.6 second (s) for the zero interleaver setting (this requires that a 0.6-s buffer be used to delay data traffic during the sync preamble transmission), 0.6 s for the short interleaver setting, and 4.8 s for the long interleaver setting. Switch S4 shall be placed in the through position during fixed-frequency operation. Referring to Fig. 3, the sequence of events for synchronous and asynchronous operation is as follows:

a. For full-duplex data operation, upon receipt of the message request-to-send (RTS) signal from the DTE, the modem shall simultaneously perform the following:

(1) return to the DTE a clear-to-send (CTS) signal,
(2) begin loading the interleaver with data traffic, and
(3) commence sending the special sync preamble pattern described in pars. 5.4.3.7.2 and 5.4.3.8.2.

b. For half-duplex (one-way reversible) data operation using radio equipment without automatic link establishment (ALE) capability, the radio set transmitter shall be keyed first, then the sequence of events shall be identical to that given for full-duplex operation.

c. Half-duplex data operation using ALE radio equipment shall incorporate a method of delaying the data CTS signal until radio link confirmation. In an example of this operation, upon receipt of the RTS signal from the user data terminal, the controller first initiates and confirms linking with the called station. During this link confirmation period, the RTS signal is controlled and delayed in the controller until the link is confirmed. After link confirmation, the controller sends the RTS signal to the modem. (In effect, the delaying of the RTS signal provides the needed delay of the data CTS signal.) Upon receipt of the RTS signal from the controller, the modem shall simultaneously perform the following:

(1) key the radio,
(2) return to the DTE a CTS signal,
(3) begin loading the interleaver with data traffic, and
(4) commence sending the special sync pattern described in pars. 5.4.3.7.2 and 5.4.3.8.2.

Figure 3. An example of equipment interface block diagram

LEGEND:

• ***: Indicates a necessary interface which is not presently defined and required in present equipments and standards, and must be incorporated.
• ANC: Automatic node controller
• AND: Logical AND, all (available) inputs must be true to obtain a true output
• CTS: Clear to send
• CTX: Clear to transmit (transmitter tuned and on)
• CTX2: CTX controlled through ANC
• DCD: Data Carrier Detect (received data carrier detection)
• DCD2: DCD controlled through ANC
• DCE: Data circuit-terminating equipment
• DTE: Data terminal equipment
• K: Indicates HF ANC control, which may also include monitoring and/or injection
• Link: HF radio link, including distant station and propagation
• OR: Logical OR, some (available) inputs must be true to obtain a true output
• Prep: Preparation to accept and send data, and key transmitter
• PTT: Push to talk (key transmitter on)
• RA: Receive audio
• RA2: RA controlled through ANC
• RC: Receive clock
• RC2: Receive clock controlled through ANC
• RCE: Radio communications equipment
• RD: Receive data
• RD2: RD controlled through ANC
• RS: Receive (HF radio) signal
• RTE: Radio terminal equipment
• RTS: Request to send
• RTS2: RTS controlled through ANC
• RTX: Request to transmit
• RTX2: RTX controlled through ANC
• Sync: Synchronization for data transmission
• TA: Transmit audio
• TA2: TA controlled through ANC
• TC: Transmit clock
• TC2: Transmit clock controlled through ANC
• TD: Transmit data
• TD2: TD controlled through ANC
• TS: Transmit (HF radio) signal
• Tune: Tuning of the transmitter system before transmit
• TX: Transmit (HF radio on and ready to send data)

5.4.2.2 Data phase. During the data phase, the transmit waveform shall contain both message information (UNKNOWN DATA) and channel probes (KNOWN DATA), that is, training bits reserved for channel equalization by the distant receive modem. Function switches S1 and S3 (fig. 2) are in the UNKNOWN DATA and DATA position, respectively, and switch S2 toggles between the UNKNOWN DATA (modified-Gray decoder (MGD) output) and the KNOWN DATA (probe) positions. The probe shall consist of zeros, D1, and D2 (D1 and D2 are defined in par. 5.4.3.7.2.1). The period of dwell in each switch position shall be a function of bit rate only. At 2400 and 4800 b/s, there shall be a 32-symbol duration in the UNKNOWN DATA position followed by a 16-symbol duration in the KNOWN DATA position. At 150, 300, 600, and 1200 b/s, the two durations shall be 20 symbols in each position. At 75 b/s, switch S2 shall remain in the UNKNOWN DATA position. Data transfer operation shall be terminated by removal of the RTS signal by the input DTE.

NOTE: In all cases, switch S2 is placed in the UNKNOWN DATA position first, following the end of the sync preamble phase.

5.4.2.3 EOM phase. When the last UNKNOWN DATA bit prior to the absence of the RTS signal has entered the forward error correction (FEC) encoder, S1 (fig. 2) shall be switched to the EOM position. This shall cause a fixed 32-bit pattern (see par. 5.4.3.1) to be sent to the FEC encoder. Function switches S2 and S3 shall continue to operate as established for the data phase.

5.4.2.4 FEC coder and interleaver flush phase. Immediately upon completion of the EOM phase, S1 (fig. 2) shall be switched to the FLUSH position causing input of flush bits (see par. 5.4.3.2) to the FEC encoder.

5.4.3 Functional descriptions. The following subparagraphs provide Fig. 2 block descriptions.

5.4.3.1 EOM sequence. The EOM sequence shall be represented by the eight-digit hexadecimal number, 4B65A5B2. The bits shall be transmitted with the most significant digit first. Thus the first eight bits are, left to right, 0100 1011.

5.4.3.2 Interleaver flush. If an interleaver is used, the duration of the flush phase shall be 144 bits (for coder flush) plus enough bits to complete transmission of the remainder of the interleaver matrix data block containing the last coder flush bit (see par. 5.4.3.4 for data block size). Flush bits shall be set to "Ø". If the interleaver is in a bypass (0.0 s) state, only the coder flush bits are transmitted.

NOTE: This causes the transmission of enough flush bits to allow effective flushing of the FEC decoder and the deinterleaver at the receiving modem.

5.4.3.3 FEC encoder. The FEC encoder shall be used for data rates up to and including 2400 b/s. The FEC encoder block diagram for fixed-frequency operation is shown on Figure 4. The FEC encoder function shall be accomplished by a single rate 1/2 constraint length 7 convolutional decoder with repeat coding used at 150 and 300 b/s. The two summing nodes on the figure represent modulo 2 addition. For each bit input to the encoder, two bits shall be taken as output from the encoder, the upper output bit T₁(x) being taken first. Coded bit streams of 4800, 2400, and 1200 b/s shall be generated for input data rates of 2400, 1200, and 600 b/s, respectively. For 300-b/s and 150-b/s input data rates, a 1200-b/s coded bit stream shall be generated by repeating the pairs of output bits the appropriate number of times. The bits shall be repeated in pairs rather than repetitions for the first, T₁(x), followed by repetitions of the second T₂(x). At 75 b/s, a different transmit format (see par. 5.4.3.7.1.1) is used and the effective code rate of 1/2 shall be employed to produce a 150-b/s coded stream. Error-correction coding shall be in accordance with Table II. For 4800-b/s fixed-frequency operation, the FEC encoder shall be bypassed.

Figure 4. FEC encoder block diagram

5.4.3.4 Interleaver load. The interleaver, when used, shall be a matrix block type which operates upon input bits. The matrix size shall accommodate block storage of 0.0, 0.6, or 4.8 s of receiving bits (depending on whether the zero, short, or long interleave setting is chosen) at all required data rates. Because the bits are loaded and fetched in different orders, two distinct interleave matrices shall be required.

NOTE: This allows one block of data to be loaded while the other is being fetched. The selection between the long and short interleaver is contained in the transmitted sync pattern (par. 5.4.3.7.2). The short interleaver shall be switch selectable to be either 0.0 or 0.6 s (see par. 5.4.3.7.2.1).

To maintain the interleave delay at a constant value, the block size shall be scaled by bit rate. Table III lists the interleave matrix dimensions (rows and columns) that shall be allocated for each required bit rate and interleave delay.

NOTE: At the rates of 300 and 150 b/s, the number of bits required for a constant time delay is the same as that for 600 b/s due to repeat coding.

Unknown data bits shall be loaded into the interleaver matrix starting at column zero as follows: the first bit is loaded into row 0, the next bit is loaded into row 9, the third bit is loaded into row 18, and the fourth bit into row 27. Thus, the row location for the bits increases by 9 modulo 40. This process continues until all 40 rows are loaded. The load then advances to column 1 and the process is repeated until the matrix block is filled. This procedure shall be followed for both long and short interleave settings.

NOTE: The interleaver shall be bypassed for 4800-b/s operation.

For operation at 75 b/s only, the following changes to the above description shall apply:

a. When the interleave setting is on long, the procedure is the same, but the row number shall be advanced by 7 modulo 20.
b. When the interleave setting is on short, the row number shall be advanced by 7 modulo 10. If the short interleaver is selected and the short interleaver setting is 0.0 s, the interleaver shall be bypassed.

5.4.3.5 Interleaver fetch. The fetching sequence for all rates shall start with the first bit being taken from row zero, column zero. The location of each successive fetched bit shall be determined by incrementing the row by one and decrementing the column number by 17 (modulo number of columns in the interleaver matrix). Thus, for 2400 b/s with a long interleaver setting, the second bit comes from row 1, column 559, and the third bit from row 2, column 542. This interleaver fetch shall continue until the row number reaches the maximum value. At this point, the row number shall be reset to zero, the column number is reset to be one larger than the value it had when the row number was last zero, and the process continued until the entire matrix data block is unloaded. For operation at the 75-b/s rate, the interleaver fetch is similar except the decrement value of the column number shall be 7 rather than 17. The bits obtained from the interleaver matrix shall be grouped together as one-, two-, or three-bit entities that will be referred to as channel symbols. The number of bits that must be fetched per channel symbol shall be a function of bit rate as given in Table IV.

5.4.3.6 Modified-Gray decoder (MGD). At 4800 and 2400 b/s, the channel bits are effectively transmitted with 8-ary channel symbols. At 1200 b/s and 75 b/s, the channel bits are effectively transmitted with 4-ary channel symbols.

NOTE: The purpose of decoding the bits from the interleaver matrix (through the MGD) is to guarantee that only one bit is in error when symbol errors involving adjacent phases are made at the receiving demodulator.

Modified-Gray decoding of the 4800-b/s, 2400-b/s (tribit), and the 1200-b/s, 75-b/s (dibit) channel symbols shall be IAW tables V and VI respectively. When one-bit channel symbols are used (600-150 b/s), the MGD does not modify the unknown data bit stream.

5.4.3.7 Symbol formation. The function of symbol formation is one of mapping the one-, two-, or three-bit channel symbols from the MGD or from the sync preamble sequence into tribit numbers compatible with transmission using an 8-ary modulation scheme. The mapping process is discussed separately for data and preamble transmissions.

5.4.3.7.1 Symbol formation for data transmission. Channel symbols shall be fetched from the interleaver only during the portion of time that unknown symbols are to be transmitted. For all data rates, the output of the symbol formation shall be scrambled with pseudorandom three-bit numbers. This scrambled waveform shall appear to be 8-ary tribit numbers regardless of operational throughput bit rates. The relationship of tribit numbers (0-7) to the transmitted phase of the waveform is further defined in par. 5.4.3.9.

5.4.3.7.1.1 Unknown data. At all rates above 75 b/s, each one-, two-, or three-bit channel symbol shall map directly into one of the 8-ary tribit numbers as shown on the state constellation diagram, Fig. 5. When one-bit channel symbols are used (600-150 b/s), the symbol formation output shall be tribit numbers 0 and 4. At the 1200-b/s rate, the dibit channel symbol formation shall use tribit numbers 0, 2, 4, and 6. At the 4800-b/s and 2400-b/s rates, all the tribit numbers (0-7) shall be used for symbol formation. At 75 b/s, the channel symbols shall consist of two bits for 4-ary channel symbol mapping. Unlike the higher rates, no known symbols (channel probes) shall be transmitted and no repeat coding shall be used. Instead, the use of 32 tribit numbers shall be used to represent each of the 4-ary channel symbols. The mapping that shall be used is given in Table VII. The mapping in Table VIIa shall be used for all sets of 32 tribit numbers with the exception of every 45th set (following the end of the sync pattern) if short interleave is selected, and every 360th set (following the end of the sync pattern) if long interleave is selected. These exceptional sets, every 45th set for short interleave and every 360th set for long interleave, shall use the mappings of Table VIIb. In any case, the resultant output is one of four orthogonal waveforms produced for each of the possible dibits of information. These values will be scrambled later to take on all 8-phase states.

NOTE: Each set consists of 32 tribit numbers. The receive modem, at rates 150 b/s and above, shall use the modification of the known data at interleaver boundaries to synchronize without a preamble and determine the correct data rate and mode of operation. At the 75-b/s rate, the receive modem shall use the exceptional set at interleaver boundaries to synchronize without a preamble and determine the correct data rate and mode of operation.

Figure 5. State constellation diagram

5.4.3.7.1.2 Known data. During the periods where known (channel probe) symbols are to be transmitted, the channel symbol formation output shall be set to 0 (000) except for the two known symbol patterns preceding the transmission of each new interleaver block. The block length shall be 1440 tribit channel symbols for short interleave setting and 11520 tribit channel symbols for the long interleave setting. When the two known symbol patterns preceding the transmission of each new interleaver block are transmitted, the 16 tribit symbols of these two known symbol patterns shall be set to D1 and D2, respectively, as defined in Table VIII of par. 5.4.3.7.2.1 and Table X of par. 5.4.3.7.2.2. The two known symbol patterns are repeated twice rather than four times as they are in Table X to produce a pattern of 16 tribit numbers. In cases where the duration of the known symbol pattern is 20 tribit symbols, the unused last four tribit symbols shall be set to 0 (000).

NOTE: When zero interleaver setting is selected, the pattern associated with the 0.6-s block is used. When 4800-b/s operation is selected, the pattern associated with the short interleaver setting is selected.

5.4.3.7.2 Sync preamble sequence.

5.4.3.7.2.1 General. The waveform for synchronization is essentially the same for all data rates. The synchronization pattern shall consist of either three or twenty-four 200-millisecond (ms) segments (depending on whether zero, short, or long interleave periods are used). Each 200-ms segment shall consist of a transmission of 15 three-bit channel symbols as described in par. 5.4.3.7.2.2. The sequence of channel symbols shall be:

0, 1, 3, 0, 1, 3, 1, 2, 0, D1, D2, C1, C2, C3, 0.

The three-bit values of D1 and D2 shall designate the bit rate and interleave setting of the transmitting modem. Table VIII gives the assignment of these values. Again, the short interleave can be selected as either 0.0 (bypassed) or 0.6 s.

NOTE: The short interleave generally should be set to 0.6 s. If the 0.0-s interleave is selected, coordination with the distant terminal must be made before transmitting data. An automatic feature of selection between the 0.0-s and 0.6-s interleaver for both transmitter and receiver is a DO.

The three count symbols C1, C2 and C3 shall represent a count of the 200-ms segments starting at 2 for the zero and short sync (interleave) setting cases and 23 for the long sync (interleave) case. The count in either case shall start at the value established by the sync case setting and count down each segment to zero. The values shall be read as a six-bit word (C1, C2, C3), where C1 contains the most significant two bits. The two-bit values of each C (C1, C2, C3) shall be converted to three-bit values. This is done by adding a "1" before the two-bit value so that this "1" becomes the most significant bit. This conversion shall be as shown in Table IX.

NOTE: The converted count of 23 (010111) would have values of 5, 5, and 7 for C1, C2, and C3, respectively.

5.4.3.7.2.2 Preamble pattern generation. The sync preamble pattern shall be a sequence of channel symbols containing three bits each (see par. 5.4.3.7.2.1). These channel symbols shall be mapped into 32 tribit numbers as given in Table X.

NOTE: When the two known symbol patterns preceding the transmission of each new interleaver block are transmitted, the patterns in Table X are repeated twice rather than four times to produce a pattern of 16 tribit numbers.

5.4.3.8 Scrambler. The tribit number supplied from the symbol formation function for each 8-ary transmitted symbol shall be modulo 8 added to a three-bit value supplied by either the data sequence randomizing generator or the sync sequence randomizing generator.

5.4.3.8.1 Data sequence randomizing generator. The data sequence randomizing generator shall be a 12-bit shift register with the functional configuration shown on Fig. 6. At the start of the data phase, the shift register shall be loaded with the initial pattern shown in Fig. 6 (101110101101 (binary) or BAD (hexadecimal)) and advanced eight times. The resulting three bits, as shown, shall be used to supply the scrambler with a number from 0 to 7. The shift register shall be shifted eight times each time a new three-bit number is required (every transmit symbol period). After 160 transmit symbols, the shift register shall be reset to BAD (hexadecimal) prior to the eight shifts.

NOTE: This sequence produces a periodic pattern 160 transmit symbols in length.

Figure 6. Randomizing shift register functional diagram

5.4.3.8.2 Sync sequence randomizing generator. The following scrambling sequence for the sync preamble shall repeat every 32 transmitted symbols:

where 7 shall always be used first and 6 shall be used last. The sequences in par. 5.4.3.8.1 and this paragraph shall be modulo 8 added to the output of the symbol formation function.

5.4.3.9 PSK modulation.

a. The eight-phase modulation process shall be achieved by assigning the tribit numbers from the scrambler to 45-degree increments of an 1800-Hz sinewave. Thus, 0 (000) corresponds to 0 degrees, 1 (001) corresponds to 45 degrees, 2 (010) corresponds to 90 degrees, etc. Figure 5 shows the assignment and pattern of output waveform generation.

NOTE: Since the transmit channel symbol duration is less than one cycle of the 1800-Hz carrier, the waveforms controlling the sine and cosine components must be filtered to prevent severe aliasing.

b. Clock accuracy for generation of the 1800-Hz carrier shall be within ±1 Hz.

5.4.4 Waveform summary. Table XI summarizes the data phase characteristics of the transmitted formats that shall be used for each bit rate.

5.4.5 Performance requirements. The measured performance of the serial (single-tone) mode, employing the maximum interleaving period, shall be equal to or better than the coded BER performance in Table XII. Performance verification shall be tested using a baseband HF simulator patterned after the Watterson Model in accordance with International Radio Consultative Committee (CCIR) 549-2. The modeled multipath spread values and fading (two sigma) bandwidth (BW) values in Table XII shall consist of two independent but equal average power Rayleigh paths. The specified values shown represent HF modem performance under ideal test conditions. To identify the minimum acceptable performance available to users, many factors, including operational test and evaluation, must be considered.